1. Field of the Invention
The present invention relates to a level shifter used in a driver circuit for a display device, and in particular, to a level shifter used in a driver circuit for a display device, the driver circuit using thin film transistors (hereinafter referred to as TFTs) formed on an insulator. It is to be noted that, in this specification, a display device means one used as an LCD (a liquid crystal display), an OLED (an organic EL display), or the like.
2. Description of the Related Art
Recently, semiconductor microfabrication technology has been advanced, which is accompanied by miniaturization of LSIs. This results in more active application of such LSIs to small-sized apparatus such as personal digital assistants, which requires lower power consumption of such LSIs. Today, LSIs driven at low power supply voltage such as 3.3 V are mainly used.
On the other hand, with regard to LCDs (liquid crystal displays) the demands for which are remarkably increasing these days in the field of personal digital assistants, monitors for computers, and the like, liquid crystal is often driven by a signal having the voltage amplitude of 10 V-20 V. Therefore, a driver circuit of such liquid crystal includes at least a circuit portion driven by high power supply voltage.
Accordingly, it is indispensable that a controller LSI using the abovementioned LSI which is driven at low power supply voltage is connected to a circuit for driving the liquid crystal which is driven at high power supply voltage through a level shifter for changing the amplitude voltage of the signal.
FIGS. 12A and 12B illustrate circuit diagrams of commonly used level shifters. It is to be noted that in this specification each power supply potential is denoted as VDD# (# is a numeral) or GND. Here, VDD1, VDD2, VDD3, and VDD4 are used wherein VDD4<VDD3<GND<VDD1<VDD2. For the sake of simplicity, GND is fixed to 0 V.
The level shifter illustrated in FIG. 12A converts an input signal having the voltage amplitude of GND-VDD1 into an output signal having the voltage amplitude of GND-VDD2. More specifically, the amplitude is converted by fixing the lower potential side and converting the potential at the higher potential side. The level shifter is structured as follows. Both of a source region of a first p-type TFT 1201 and a source region of a second p-type TFT 1202 are connected to the power supply VDD2. A drain region of the first p-type TFT 1201 is connected to a source region of a third p-type TFT 1203, and a drain region of the second p-type TFT 1202 is connected to a source region of a fourth p-type TFT 1204. A drain region of the third p-type TFT 1203 is connected to a drain region of a first N type thin film transistor (hereinafter referred to as an n-type TFT) and a gate electrode of the second p-type TFT 1202. A drain region of the fourth p-type TFT 1204 is connected to a drain region of a second n-type TFT 1206 and a gate electrode of the first p-type TFT 1201. Both of a source region of the first n-type TFT 1205 and a source region of the second n-type TFT 1206 are connected to GND (=0 V). An input signal (In) is input to a gate electrode of the third p-type TFT 1203 and a gate electrode of the first n-type TFT 1205. An inverted signal of the input signal (Inb) is input to a gate electrode of the fourth p-type TFT 1204 and a gate electrode of the second N-type TFT 1206. An output signal (Out) is taken out from the drain region of the fourth n-type TFT 1204. Here, an inverted output signal (Outb) can also be taken out from the drain region of the third p-type TFT 1203.
It is to be noted that, though there are n-type and p-type as the conductive types of a TFT, in this specification, in the case where the polarity of a TFT is not specifically limited, the conductive types are described as a first conductive type and a second conductive type. For example, when the first conductive type TFT is of the n-type, the second conductive type means the p-type. Conversely, when the first conductive type TFT is of the p-type, the second conductive type means the n-type.
Next, basic operation of the conventional level shifter is described. When an Hi signal is input as the input signal (In), the n-type TFT 1205 is in a conductive state while the p-type TFT 1203 is in a nonconductive state. Therefore, a signal having the potential of GND, that is, an Lo signal, is input to the gate electrode of the p-type TFT 1202, and the p-type TFT 1202 is in a conductive state. On the other hand, here, the inverted input signal (Inb) is an Lo signal. Therefore, the n-type TFT 1206 is in a nonconductive state while the p-type TFT 1204 is in a conductive state. Since both of the p-type TFTs 1202 and 1204 are in a conductive state, an Hi signal is outputted as the output signal (Out) with the potential of VDD2. It is to be noted that the p-type TFT 1201 is in a nonconductive state, which assures that the potential of the gate electrode of the p-type TFT 1202 is held at Lo=GND.
When the potential of the input signal (In) is Lo, since the level shifter illustrated in FIG. 12A is structured to be symmetrical, an Lo signal is outputted from the output terminal (Out) with the potential of GND, that is, 0 V.
In this way, an input signal having the voltage amplitude of GND-VDD1 is converted into an output signal having the voltage amplitude of GND-VDD2.
Next, the level shifter illustrated in FIG. 12B converts an input signal having the voltage amplitude of VDD3-GND into an output signal having the voltage amplitude of VDD4-GND. More specifically, the amplitude is converted by fixing the higher potential side and converting the potential at the lower potential side. The level shifter is structured as follows. Both of a source region of a first n-type thin film transistor (hereinafter referred to as an n-type TFT) 1211 and a source region of a second n-type TFT 1212 are connected to a power supply VDD4. A drain region of the first n-type TFT 1211 is connected to a source region of a third n-type TFT 1213, and a drain region of the second n-type TFT 1212 is connected to a source region of a fourth n-type TFT 1214. A drain region of the third n-type TFT 1213 is connected to a drain region of a first p-type thin film transistor (hereinafter referred to as a p-type TFT) 1215 and a gate electrode of the second n-type TFT 1212. A drain region of the fourth n-type TFT 1214 is connected to a drain region of a second p-type TFT 1216 and a gate electrode of the first n-type TFT 1211. Both of a source region of the first p-type TFT 1215 and a source region of the second p-type TFT 1216 are connected to GND (=0 V). An input signal (In) is input to a gate electrode of the third n-type TFT 1213 and a gate electrode of the first p-type TFT 1215. An inverted signal of the input signal (Inb) is input to a gate electrode of the fourth n-type TFT 1214 and a gate electrode of the second p-type TFT 1216. An output signal (Out) is taken out from the drain region of the fourth n-type TFT 1214. Here, an inverted output signal (Outb) can also be taken out from the drain region of the third n-type TFT 1213.
Next, basic operation of the conventional level shifter is described. When an Lo signal is input as the input signal (In), the p-type TFT 1215 is in a conductive state while the n-type TFT 1213 is in a nonconductive state. Therefore, a signal having the potential of GND, that is, an Hi signal, is input to the gate electrode of the n-type TFT 1212, and the n-type TFT 1212 is in a conductive state. On the other hand, here, the inverted input signal (Inb) is an Hi signal at this time. Therefore, the p-type TFT 1216 is in a nonconductive state while the n-type TFT 1214 is in a conductive state. Since both of the n-type TFTs 1212 and 1214 are in a conductive state, an Lo signal is outputted as the output signal (Out) with the potential of VDD4. It is to be noted that the n-type TFT 1211 is in a nonconductive state, which assures that the potential of the gate electrode of the n-type TFT 1212 is held at Hi=GND.
When the potential of the input signal (In) is Hi, since the level shifter illustrated in FIG. 12B is structured to be symmetrical, an Hi signal is outputted from the output terminal (Out) with the potential of GND, that is, 0 V.
In this way, an input signal having the voltage amplitude of VDD3-GND is converted into an output signal having the voltage amplitude of VDD4-GND.
A problem with regard to the level shifters illustrated in FIGS. 12A and 12B is now described. It is to be noted that, since the problem is common to the level shifters illustrated in FIGS. 12A and 12B, only the one illustrated in FIG. 12A is described by way of example. As described in the above, today, controller LSIs operating at 3.3 V are mainly used. Suppose the level shifter illustrated in FIG. 12A carries out conversion in case of VDD1=3 V and VDD2=10 V. When the amplitude of the input signal to the TFTs 1203, 1204, 1205, and 1206 is 3 V and the threshold voltage of the n-type TFTs 1205 and 1206 is 3 V, the level shifter is not expected to operate normally. More specifically, since, as the voltage amplitude before conversion becomes smaller, the gate-source voltage becomes less likely to be high enough to make the TFTs sufficiently conductive, normal operation becomes more difficult.